Addressing Criticism of RISC-V Microprocessors

Is RISC-V just a rehash of 1980s RISC ideas? Requires too many instructions to do simple stuff?

RISC-V is an instruction-set architecture (ISA) for microprocessors which people seem to either love or hate. In particular there seem to bit of rivalry between the ARM and RISC-V camp developing.

It is perhaps not without reason. RISC-V and ARM represent quite radically different philosophies about how a RISC chip should be designed. RISC-V is taking a very long term view with a strong emphasis on simplicity and not painting yourself into a corner due to choices which have short term benefit, but may cause long term problems. RISC-V really embrace the philosophy of RISC, in terms of keeping things really simple with not only a minimal instruction-set but also one dominated by simple instructions.

ARM is more of a ruthlessly pragmatic design choice. Choices are made based on what makes sense today and in the near future in terms of what we are currently capable of doing in hardware. ARM design does not shy away from adding fairly complex instructions if those are believed to improve overall performance.

Hence ARM has numerous instructions which each do quite a lot of work. ARM has instructions for complex addressing modes as well as conditional execution instructions (32-bit ARM only). These instructions are executed if a condition is true, allowing us to avoid branches.

There are merits to both approaches. When criticizing one design it is useful to get the facts straight. For RISC-V there are a lot of misconceptions which I want to set straight. I will try to cover some of the more popular ones I have encountered.

Myth 1: RISC-V Instruction-Set Bloats Programs

RISC-V instruction typically do a lot less than ARM instructions. ARM has an instruction LDR for loading data from memory into a register. It is designed to be able to handle typical C/C++ code like this:

// C/C++ code
int  a = xs[i];

We want to pull data at index i out from an array xs. We can translate this into ARM code where register x1 holds the start address of array xs and register x2 holds…