Anything is possible but I consider that highly unlikely. This is from the RISC-V reader written by David Patterson and Andrew Waterman. If they screwed up something that basic, it would have been an utter embarrassment to them.

As far as In understand this is both CPUs configured to be similar. E.g. both configured with 12 KB cache.

Also it would have been rally odd for RISC-V designers to be promoting RISC-V due to its ability to have lower transistor count if that was not the case. They have spent 10 years or so desingning RISC-V and one of the design goals was to get the transistor count down to save money. Having much smaller instruction-set helps you achieve that when you are at the lower end.

For massive out-of-order processors with huge caches, the difference will likely be marginal.