ARM vs RISC-V Vector Extensions

A comparison of the RISC-V vector extension (RVV) and ARM scalable vector extension (SVE/SVE2).

Microprocessor with vector instructions is going to be the big thing for the future. Why? Because self-driving, speech recognition, image recognition are all based on machine learning and machine learning is all about matrices and vectors.

But that is not the only reason. We have been banging our heads in the wall trying to eke out more performance for years ever since we semi-officially declared Moore’s laws to be over. In the golden old days of microprocessor design, we could simply double the clock frequency of the CPU each year and boom everybody was happy. That wonderful old trick is over.

Performance increases has been stalling, creating a need to utilize more transistors for parallel processing in different ways, whether multi-core, vector-processing or out-of-order execution.

Today we play a thousand different clever games to eek out more performance whether that is through adding more CPU cores, adding out-of-order execution, more advance branch predictors or SIMD instructions.

All of these tricks really boil down to one central idea: Trying to find ways of doing work in parallel. Whenever you loop over an array of elements and do some computation on each of these…