Demystifying RISC Microprocessor Philosophy
Deep misconceptions between RISC and CISC processor still remain. Let us try to clarify.
I write a lot about microprocessors where I talk briefly about RISC and CISC processors. It is a topic that naturally pops up now that RISC processors such as those based on Arm and RISC-V are on the rise while CISC processors based on the x86 instruction-set architecture are in a relative decline.
From some of the feedback I get I realize that even people who are quite well read on the topic have deep misconceptions about what makes a processor a RISC or CISC processor.
I wrote about how old CISC instruction-sets such as those found on x86 processors don’t really offer any kind of performance advantage over modern RISC instruction sets. This produced the following response:
It is mathematically logical that a CPU (i486) that can on average execute RISC instructions in a single clock cycle — and on top of that can also execute CISC instructions in multiple cycles — is by definition inherently superior to a RISC processor.
This response gives a good starting point to discussing a number of RISC-CISC misconceptions. Professor David A. Patterson made the case for RISC in the paper: The Case for the Reduced Instruction Set…
