I don’t know all the details but the RISC-V designers specifically write about context switching having been a problem that made others avoid it in the past. However the issue they discussed was saving and restoring of large vector registers.
Their solution is to have all vector registers disabled by default and only save and restore enabled registers.
I assume that when the OS interrupts in the middle of a vector setup it will save to stack the current vector length as well as content of active vector registers.
When switching context back you will simply have to pop this stored state from the stack.
Might even be cheaper than SIMD. I don’t know how SIMD extensions currently work but I assume they must be stored on the stack during context switch. With large SIMD registers that may be expensive too.
I don’t think the RISC-V P extension which adds SIMD has this problem as it reuses the general purpose registers.