I found the Jim Keller interview you talked about. Great talk: https://www.youtube.com/watch?v=yTMRGERZrQE

I think discussing what he said could easily turn into something akin to scripture debate. You know when two people are convinced the full truth is in scripture and it is all about proving your point by interpreting what the oracle said.

My interpretation of what Keller said on fixed vs variable length instructions is that broadly speaking across the history of the industry it hasn't mattered much. You could find workarounds.

Yet if you look at what he said about RISC-V it is clear I think that he understand that while you can solve any problem, some problems are easier and quicker to solve. A simpler instruction-set architecture will make your job to optimize easier. That means you can get a product out of the door ahead of the competition. By the time they caught up you got something new out the door.

Intel has been managing to win race for years because they had more talent and more money to throw at the problem. Thus having a slightly harder problem didn't matter.

Now Intel is facing companies such as Apple and Nvidia with just as deep pockets as them. When that is the case then I think those with the easier problem to solve will be more likely to stay ahead of the game each year.

You make a lot of good points I agree with, but I don't quite get the rational behind your argument around RISC-V and ML cores for Apple and Nvidia.

Neither Apple nor Nvidia expose the machine code opcodes for their specialized ML hardware. Thus going RISC-V would not hurt their performance. Developers are going to use their hardware through some driver or library anyway which Nvidia and Apple themselves will write.

And why would you want to run "regular code" on specialized ML hardware? Regular code doesn't run on an Nvidia GPU today. You got to write fairly specialized code using CUDA.

You talk about the difference between x86 and Arm is just about the decoder but an ISA impose far more your micro-architecture. Depending on your ISA you may have a lot of state to manage. That adds complexity to your superscalar OoO engine. It adds complexity to your pipeline. So the extra transistor count is not limited to the decoders.

Why else do you think Jim Keller says he could speed up RISC-V more easily? Because there is less in the ISA inducing complecity in the micro-architecture.

I am totally onboard with his RISC-V take though. Arm has gotten fairly complex as well. RISC-V is definitely a lot easier to work with. But all of that is reflected in most of my writing. I have written a lot more positive articles about RISC-V than Arm.