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Random Facts About ARM, x86, RISC-V, AVR and MIPS Microprocessors

Interesting technical differences and features of today’s popular microprocessors (CPUs)

ARM Can Conditionally Execute Single Instructions

CMP AX, 42
JE equal
MOV BX, 12
JMP done
equal:
MOV BX, 33
done:
NOP
CMP    r6, #42
LDREQ r3, #33
LDRNE r3, #12
SUBS r3, r6, #42
ADDEQ r3, #33
ADDNE r3, #12

Why Does ARM have Conditional Execution?

RISC-V Does Not Have Conditional Execution

MIPS and RISC-V Don’t have Status Flags

CMP AX, 42
JE equal
BEQ x1, x2, equal
BGT rs, rt, offset // branch if rs > rt
BLT rs, rt, offset // branch if rs < rt
BEQ $t0, $t1, offet # branch if $t0 == $t1
BGEZ $t0, offset # branch if $t0 ≥ 0

MIPS, RISC-V and ARM A64 Have a Register Which is Always ZERO!

BGEZ rs, offset
BGE rs, x0, offset
NEG rd, rs
SUB rd, x0, rs // rd = x0 - rs = 0 - rs
MOV x1, 42
ORR x1, xzr, 42
x1 ← xzr || 42
LI x1, 42
ADDI x1, x0, 42
MV x1, x2
ADDI x1, x2, 0

MIPS is very Popular for Teaching, But Why?

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A PIC32 in DIP package running using the MIPS instruction set placed on a a white breadboard for easy prototyping. It is programmed with a Arduino board (blue).

AVR was Designed by two Students in Trondheim, Norway

RISC-V has Extendible Instruction Set

Functional Thinking in Assembly Instruction Sets

Geek dad, living in Oslo, Norway with passion for UX, Julia programming, science, teaching, reading and writing.

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