John L. Hennessy one of the pioneers of RISC and part of RISC-V says you can do compressed instruction decoding without separate decoders. That it just works like a regular RISC-V extension.

Regarding traps, I don't see how this would work on other processors. x86 and ARM doesn't have a minimal instruction-set which you are required to implement. So if an instruction is not implemented, then how do you know what instructions you can use to implemen that missing instruction?

You dont' have a clearly defined minimum-set of instructions which must exist. So I am unconvinced of this claim.

If I pulled out 1000 random instructions from x86 and tried to run current software on it, I am pretty sure it wouldn't work.

I have never suggested RISC-V does anything which has not been done in some form before. The point is that RISC-V has the benefit of creating a clean and coherent design based on learning from the past.

That is valuable even if it was not free. You see the the exact same thing with programming languages. Plenty of good modern languages don't offer new features. The "feature" is throwing out all the old garabage that no longer makes sense to make a cleaner, more effective and easier to learn and use language. RISC-V IMHO is much the same. It is akin to the Golang of microprocessors.