RISC-V Assembly Code Examples

Learning RISC-V Assembly code trough simple examples and exercises

A lot of RISC-V example code jumps straight into fairly complex code examples. I intend to start slow do some very simple examples.

For a proper introduction to things such as registers, conditional branching and assembly code format, I advice reading: RISC-V Assembly for Beginners.

That is an overview story, but does not contain that many examples. As with the first article we will use the online Cornell University RISC-V interpreter.

When working through the code examples, you could print out this RISC-V reference sheet to help you: James Zhu’s RISC-V Reference.

The most important instructions are probably:

• ADDI rd, zero, immediate, to load a value (immediate) into register rd.
• LW rd, offset(rs1) to load content at memory location offset + rs1 into register rd.
• SW rd, offset(rs1) store content of rd register at memory location offset + rs1.
• ADD rd, rs1, rs2 to content of two registers and store value in destination register rd.
• The branch instructions BEQ, BNE, BLT. Read previous story for more details.

Input Doubler