RISC-V seems to gaining ground in the coprocessor area though, where you would have used a custom ISA anyway with amost no tool support.

I think this is a bit different than writing applications and OS kernels. It will likely be much smaller specialized code, which likely goes into drivers.

My understanding is that the RISC-V base instruction set is made so that if your CPU doesn't support a particular extension, the compiler can generate equivalent code using the base instructions.

Stuff will still work, it simply will not run as fast as using specialized instructions would.