Thanks for the feedback Jamie, I keep learning something new age time I visit this topic from the feedback I get.

It is like Elon Musk says: You are always wrong. It is just a question of trying to be less wrong over time.

It seems like I need to dive into pipelining and read up on the history there. You seem to have given me some good pointers to start.

I do remember reading about the delay slots you mentioned though. They keep talking about that as kind of a mistake in the MIPS design, when they discuss the newer RISC-V instruction-set.

So let me think out loud about pipelining. I am curious about your thoughts. Based on Patterson paper it seemed like pipelining was a known concept back then. Cray-1 in 1976 had a form of pipelining for vector processing. But it didn’t have a CPU in a single package (Silicon die).

Could it be they when Patterson wrote the paper, pipelines only existed in mainframe computers or minicomputers and not microchip based computers?

You mentioned 6502 as an exception but perhaps a classic RISC 4-5 step pipeline could at that point not fit on a microchip?

Or perhaps 6502 could do it because it was such a simple design? It had very little state to manage as far as I understand with just an accumulator and two index registers.

It also just had 56 instructions. I imagine that for more complex chips with more instructions and registers, you might not be able to fit a pipeline on a single microchip?

Any thoughts? I am just trying to come up with questions to explore further. I like studying these concepts by formulating some hypothesis and then attempt to verify or disprove it.