The Case for RISC-V on Desktops and Servers

Is RISC-V only for embedded systems, or can it compete on the desktop and server rooms as well?

The base RISC-V instruction set RV32I is just 47 instructions. That is what allows you to build RISC-V CPUs with half the die area of an ARM CPU for the embedded space. That translates into 4x lower cost when producing similar volumes. Why? Because cost is the square of the die area.

It can be tempting to conclude from this that RISC-V has no advantages in the server and desktop space. If you are going to have desktop class computing you are going to need more instructions right? Sure but not nearly as many as you think. ARMv8 (64-bit ARM) has about 1000 instructions and x86–64 has about 1500 instructions. 32-bit ARM is around 500.

A desktop class RISC-V chip does not get anywhere near that. If you add all the standard extensions, M, A, F and D you get the RV32IMAFD instruction set abbriviated as RV32G. This only has 122 instructions. What about the 64-bit version, RV64G? That only adds 9 instructions. We could even add the vector extension V. That is around 50 instructions. Regardless you still don’t get anywhere near the instruction count of x86 and ARM despite offering desktop and server style functionality.

However it could be argued that once you make desktop class chips the size of your ISA doesn’t matter much. That is true. The number of transistors you need to allocate to making an efficient…