The Genius of RISC-V Microprocessors

How the instruction set for RISC-V processors has been designed cleverly for both simplicity and high performance.

Erik Engheim
14 min readDec 15, 2020


Since the RISC and CISC wars that raged in the late 1990s, people have claimed that RISC and CISC doesn’t matter anymore. Many will claim that instruction-sets are irrelevant.

But instruction-sets matter. They put limits on what kind of optimizations you can easily add to a microprocessor.

I have lately been learning more about the RISC-V instruction-set architecture (ISA) and here are some of the things which really impress me about the RISC-V ISA:

  1. It is a RISC instruction set which is small and easy to learn (47 in base). Very favorable to anyone interested in learning about microprocessors. RISC-V Cheat Sheet.
  2. Dominant architecture used for teaching digital design in universities: Why Universities Want RISC-V.
  3. It is cleverly designed to allow CPU builders to create high performance microprocessors using a RISC-V ISA.
  4. With no license fees and being designed to allow simple hardware implementations, a dedicated hobbyist could in principle make his own RISC-V CPU design in reasonable time.
  5. Open Source designs readily available to modify and play with: The Berkely Out-of-Order (BOOM) RISC-V Processor.

Read more: What Is Innovative About RISC-V?

The Revenge of RISC

As I have begun to understand RISC-V better, I realize that RISC-V is a radical shift back to what many thought was a bygone era of computing. In terms of design, RISC-V is almost like taking a time machine back to the classic Reduced Instruction Set Computer (RISC) of the early 80s and 90s.

Many have remarked over the latter years that the RISC and CISC distinction no longer matters because RISC CPUs such as ARM has added so many instructions, many fairly complex, that it is more of a hybrid today than a pure RISC CPU. Similar sentiments are uttered about other RISC CPUs such as PowerPC.

RISC-V in contrast is really hard core about being a RISC CPU. In fact if you read discussion online about RISC-V…



Erik Engheim

Geek dad, living in Oslo, Norway with passion for UX, Julia programming, science, teaching, reading and writing.