They are tied a bit together. The idea with RISC is that you create an instruction-set which is made so that the inside can be made simple.

The idea was that if you have e.g. instruction of regular size which all execute in the same number of step, you could easily pipeline them. Hence pipelining got assocated with RISC. But of course nothing stops you from pipelining a CISC processor. It will simply be a lot more work.

That was the argument David Patterson made: If we make the design simpler we can get pipelines before the CISC guys because they will be much easier to design.

If you make decoders in a CISC which breaks up complex instructions into simpler micro-operations then a lot of the interior can look more RISC-like, but you still had to add a lot more complex decoders to do that. Also in practice the piplines will not work as well. It is harder to break up instructions which was not designed to neatly fit into a pipeline.

CISC instructions were not designed for superscalar architectures or pipelining. But they can just throws lots of transistors at the problem to work around it. That is why the difference between RISC and CISC is less noticable for really big powerful chips.

The big difference between RISC and CISC you really see with smaller chips. That is why for simpler chips RISC dominates completely. Nobody would make a small CISC chip today.