To address CISC decoding paragraphs. Could you be a bit more specific? I don't know what you are getting at.

I never meant to cover every possible detail about microprocessors. I have several other stories covering other aspects.

This one was meant to be focused on the parts that help understand the difference between RISC and CISC microprocessors.

I don't see the relevance of proper timings, excessive details about pipelines and opcode fusion. It is not meant to be a primer on x86 architecture.

Nor is the added registers in x86_64 of any relevance as far as I can tell. I mean it is great for anybody writing x86 assembly code, but isn't very illuminating with respect to what differentiates RISC from CISC.

Not clear to me about the point you are making about SIMD. Sure it affects performance but what does that have to do with article trying to clarify the difference between RISC and CISC processors?

Both RISC and CISC processor could have SIMD instructions. Although you could argue there are more RISC ways of going about this. You could read my article about RISC-V vector extensions for a more in depth discussion of this: https://medium.com/swlh/risc-v-vector-instructions-vs-arm-and-x86-simd-8c9b17963a31