You are making an apples to oranges comparison. The idea of RISC-V is to not pay for what you don't use. I you want to make a simple micro-controller to control say a motor or other electronic equipment, then I don't need instructions for cryptography, vector processing, JavaScript, operating systems with different privilege levels etc.

For simple microcontrollers with relatively few transistors, supporting those instructions are going to gobble up your transistor budget. That is why you see RISC-V chips for embedded markets requiring less than half the number of transistors compared to an ARM chip.

The point of RISC-V extensions is to only pay for what use. If you particular application does not need encryption, you don't pay for it in terms of transistors.

Your keyboard, your car, motor controllers, mouse etc all use a variety of small chips. Instead of inventing entirely new chip designs to deal with these tasks people can use customized RISC-V architectures because you then have a ready made toolchain to develop those chips and test software running on them.

What do think is the better solution: Put a RISC-V chip with 50 instructions in your keyboard or an ARM chip with 1000 instructions? The latter will add a lot of costs while making your keyboard no better.

Next example: You are building an ML accelerator. You need tons of cores doing vector processing to handle large matricies. What ISA will these cores use?

With RISC-V you can add the base 47 instructions plus the vector extension. Now you got everything to make a small core, you can duplicate 1000x over.

You think all these cores meant to accelerate machine learning needs cryptography instructions? Of course not. They have a pretty narrow task to do: Compute lots of matrix operations very fast.

RISC-V can be taylored to all sorts fo specialized chips due to its extensions. Sure you can invent your own custom instruction-set. However the is idiotic, as it is actually a tricky thing to do and you would have to build all your tools and software yourself to run tests, diagnostics, benchmarking and analysis. Hardware companies are seeing how RISC-V is saving them a lot of time by providing a standard set of tools and an already well thought out base instruction-set.

You ask me: What if a RISC-V processor has a bug... yeah what then indeed?

Bug in what? The instruction-set architecture? You seriously think a bug in the x86 or ARM ISA would be any less of a problem. You don't call up ARM in the middle of the night and tell them there is a bug in the ISA, and they rush out to patch the silicon of a 6 billion chips delivered earlier.

This is hardware, not software. You don't just download an update. What if there is a problem in the micro-architecture? Well then you call the company which desinged that RISC-V micro-architecture. You know, you can buy ready RISC-V designs.

Can there be flaws in the RISC-V ISA? Of course, and it can be in x86 and ARM as well. However RISC-V instructions are evaluated in public with feedback. I think the chance of RISC-V instructions having bugs is frankly less, for the same reason that open source software tends to have fewer bugs.